The present invention relates to a graphics plotting apparatus which includes a logic circuit block and a memory block of a large storage capacity such as a DRAM (Dynamic Random Access Memory) both mounted on a common semiconductor chip and which implements three-dimensional graphics plotting and, more particularly, to an arrangement of various functioning blocks in a graphics plotting apparatus for augmenting the performance of the entire apparatus.
A graphics plotting image processing apparatus is conventionally known which uses, in addition to an external memory block which is known, a large capacity memory such as a DRAM built in a chip in which a plotting logic circuit is built.
An aimed plotting performance can be comparatively and readily obtained from performances of semiconductor devices in recent years. Therefore, a two-dimensional graphics plotting processing apparatus is configured simply such that, alongside and in the proximity of a graphics plotting processing logic circuit, which is used conventionally, a DRAM core having a control mechanism equivalent to that for a DRAM for universal use is disposed, and the graphics logic plotting processing logic circuit and the DRAM core are connected to each other by a single bus.
Also, a block which performs two-dimensional graphics plotting processing is designed, using a technique such as a gate array, without taking a positional relationship of various processing blocks into consideration in order for the area to take precedence.
In recent years, however, where it is intended to construct a three-dimensional graphics plotting image processing apparatus, even if the capabilities of semiconductor devices are made the most of, further augmentation of the performance is still demanded.
On the other hand, if a three-dimensional graphics plotting image processing apparatus is constructed so as to minimize the area without placing a stress on the performance as with such a two-dimensional graphics plotting processing logic circuit as described above, then not such an arrangement method wherein individual logical blocks are divided into corresponding physical blocks as seen in FIG. 18A but such an arrangement method as illustrated in FIG. 18B is used. In particular, a functioning block 1 is not divided into a host interface block 2, an input buffer block 3, a straight line plotting setup block 4, a straight line plotting block 5 and a display control block 6 as seen in FIG. 18A. Rather, the logic circuits just mentioned are collected into a single block and laid out as a single physical block 8 as seen in FIG. 18B using a gate array technique.
However, in a three-dimensional graphics plotting process, much importance is attached, in particular, to the performance. Therefore, both optimum division of a processing system into blocks and optimum arrangement of the blocks are significant.